1. Field of the Invention
The present invention relates generally to methods for filling shallow trenches with trench fill layers within integrated circuits. More particularly, the present invention relates to methods for filling shallow isolation trenches with trench fill dielectric layers within integrated circuits.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
In integrated circuit technology, it is necessary to separate the active regions containing active devices from one another. In early bipolar integrated circuits, the active regions were generally electrically isolated from each other by PN junctions. However, with increasing demand for higher device densities, it has become necessary to reduce the isolation areas.
As integrated circuit device dimensions have decreased, it has become increasingly common within advanced integrated circuit technology to employ trench isolation methods, such as shallow trench isolation methods, and recessed oxide isolation methods, to form trench isolation regions nominally coplanar with adjoining active semiconductor regions of semiconductor substrates. Trench isolation regions nominally coplanar with active semiconductor regions within semiconductor substrates are desirable since they optimize, when subsequently forming patterned layers upon those nominally coplanar trench isolation regions and active semiconductor regions, the limited depth of focus typically achievable with advanced photo exposure tooling.
Various techniques are known to produce trench isolation. U.S. Pat. Nos. 5192,706 and 5702,977 describe techniques for fabricating trench structures. these patents are primarily concerned with preserving a planar top surface configuration when the sizes of the trench structures vary widely in size. U.S. Pat. No. 5,521,422 describes in detail the parasitic leakage problem associated with very small trench isolation structures, and proposes structures for reducing leakage.
In very small semiconductor geometries, junction leakage seems to play a dominate killer for 0.18 um CMOS and beyond. For this reason it is important to develop new trench isolation structures and methods of fabrication that will eliminate or reduce the leakage associated with present structures.